1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory capable of electrically erasing data and, more particularly, to a semiconductor memory capable of improving reliability by shortening a voltage stress time of each non-selected cell and preventing erroneous erasure.
2. Description of the Related Art
In comparison with ultraviolet-erasable type EPROMs, EEPROMs (Electrically Erasable and Programmable ROMs) from which stored data can be electrically erased and in which new data can be written are easy to use. For example, data can be erased by electrical signals in a state wherein an EEPROM is kept mounted on a board. Therefore, the demand for EEPROMs to be used for control operation, IC cards (memory cards), and the like has greatly increased. EEPROMs capable of realizing a large capacity employ a memory cell having an arrangement shown in FIGS. 1A to 1C are especially popular.
FIG. 1A is a plan view of a pattern; FIG. 1B, a sectional view taken along a line A1-A2 in FIG. 1A; and FIG. 1C, a sectional view taken along a line B1-B2 in FIG. 1A. Referring to FIGS. 1A to 1C, reference numeral 11 denotes a floating gate consisting of a first polysilicon layer; 12, an erasing gate consisting of a second polysilicon layer; 13, a control gate consisting of a third polysilicon layer, which is also used as a word line of the memory cell; 14, a p-type substrate; 15 and 16, a source and a drain formed on the substrate 14, respectively; 17, a contact hole; 18, a data line consisting of an aluminum layer connected to the drain 16; 19, a gate insulating film of a floating gate transistor portion; 20, a gate insulating film formed between the floating gate 11 and the erasing gate 12 and 21, a gate insulating film formed between the floating gate 11 and the control gate 13. The gate insulating film 21 is constituted by a three-layer film of an O-N-O (Oxide-Nitride-Oxide) structure. In addition, reference numeral 22 denotes a gate insulating film formed between the erasing gate 12 and the control gate 13 and having an O-N-O structure; 23, a gate insulating film of a selection transistor portion using the third polysilicon layer as a gate electrode; 24, a field insulating film; and 25, an insulating interlayer.
FIG. 2 shows an equivalent circuit of the memory cell shown in FIGS. 1A to 1C. FIG. 3 shows an equivalent circuit of a capacitance system. Referring to FIG. 2, reference symbol V.sub.D denotes a drain voltage; V.sub.S, a source voltage; V.sub.FG, a floating gate voltage; V.sub.EG, an erasing gate voltage; and V.sub.CG, a control gate voltage. Referring to FIG. 3, reference symbol C.sub.FC denotes a capacitance between the floating gate 11 and the control gate 13; C.sub.FE, a capacitance between the floating gate 11 and the erasing gate 12; C.sub.FD, a capacitance between the floating gate 11 and the drain 16; and C.sub.FS, another capacitance with respect to the floating gate 11 between floating gate 11 and source 15. In this capacitance system, an initial value Q(.sub.1) of a charge amount corresponding to all the capacitances can be given by the following equation: EQU Q.sub.(1) =(V.sub.FG -V.sub.CG).multidot.C.sub.FC +(V.sub.FG -V.sub.EG).multidot.C.sub.FE +(V.sub.FG -V.sub.D).multidot.C.sub.FD +(V.sub.FG -V.sub.S).multidot.C.sub.FS ( 1)
If the sum of all the capacitances is represented by C.sub.T, then EQU C.sub.T =C.sub.FC +C.sub.FE +C.sub.FD +C.sub.FS ( 2)
Therefore, the voltage V.sub.FG to be applied to the floating gate is given by the following equation: EQU V.sub.FG ={(V.sub.CG .multidot.C.sub.FC +V.sub.EG .multidot.C.sub.FE +V.sub.D .multidot.C.sub.FD +V.sub.S .multidot.C.sub.FS)/C.sub.T }+{Q(1)/C.sub.T } (3)
Substitutions of Q.sub.(1) /C.sub.T =V.sub.FG(1) and V.sub.S =0 V into equation (3) yield: EQU V.sub.FG ={V.sub.CG .multidot.C.sub.FC +V.sub.EG .multidot.C.sub.FE +V.sub.D .multidot.C.sub.FD)/C.sub.T }+V.sub.FG(1) ( 4)
The memory cells described above are arranged in an actual memory to form a matrix. In this case, however, in order to simplify description, a 4-bit memory cell array, shown in FIG. 4, will be considered. FIG. 4 is a circuit diagram of a memory cell array having memory cells M1 to M4. The drains of these four memory cells M1 to M4 are connected to either of two data lines DL1 and DL2. Their control gates are connected to either of two word lines WL1 and WL2. The erasing gates of all the memory cells M1 to M4 are commonly connected to an erase line EL. A reference voltage of, e.g., 0 V is applied to their sources. Data erasure of the memory cell array having the abovedescribed arrangement is performed in the following manner. Data erasure is collectively performed in all the memory cells M1 to M4. For this reason, the source potential V.sub.S, the drain potential V.sub.D, and the control gate potential V.sub.CG of each memory cell are set to 0 V (i.e., the data lines DL1 and DL2 and the word lines WL1 and WL2 are set to 0 V), and the erasing gate potential V.sub.EG is set to a high potential of, e.g., 20 V. At this time, electrons in the floating gates are emitted into the erasing gates upon field emission due to the Fowler-Nordheim tunnel effect, and the floating gates are charged and set at a positive potential. Therefore, if the potential VFG(1) in each floating gate is set to, e.g., +3 V (a threshold value V.sub.TH of each floating gate transistor is set to be 1 V), an inversion layer is formed under the floating gate, and the threshold voltage of each memory cell is decreased. This state will be referred to as a data state of "1".
A case wherein data is written in one memory cell, e.g., the memory cell M1 of the memory cell array will be considered below. When data is to be written in the selected memory cell M1, the control gate potential V.sub.CG of the memory cell M1, i.e., the word line WL1, is set at a high potential of, e.g., +12.5 V, the drain potential V.sub.D, i.e., the data line DL1 is set at a high potential of, e.g., +10 V, and the source potential V.sub.S and the data and word lines DL2 and WL2 are set at 0 V. In addition, a power source voltage of +5 V, for example, is applied to the erasing gate. With this operation, the potential of the floating gate of the selected memory cell is increased due to the capacitance ratio of the erasing gate, and hence an easy-to-write state is obtained. As a result, the hot electron effect occurs near the drain of the selected memory cell M1, and electrons which are generated upon impact ionization are injected in the floating gate. Since the potential of the floating gate is negative in this state, if the potential V.sub.FG (1) in the floating gate is set at, e.g., -3 V, the threshold voltage of the memory cell is increased. This state will be referred to as a data state of "0". No hot electron effect occurs at the non-selected memory cells M2 to M4.
Voltage stresses acting on the non-selected cells M2 to M4 in each data state, i.e., data state of "1", "0" during a data write operation will be considered. Since the values V.sub.EG .multidot.C.sub.FE and V.sub.D .multidot.C.sub.FD in equation (4) in the write mode are sufficiently small as compared with the value V.sub.CG .multidot.C.sub.FC, equation (4) in the write mode can be rewritten as follows: EQU V.sub.FG =(C.sub.FC /C.sub.T).multidot.V.sub.CG +V.sub.FG(1)( 5)
Assume that a capacitance ratio C.sub.FC /C.sub.T is set to be, e.g., 0.6, and that a memory cell with a data state of "1" has V.sub.FG(1) =+3 V and a memory cell with a data state of "0" has V.sub.FG(1) =-3 V. In addition, assume that the non-selected cell M2 on the same word line WL1 as that of the selected cell M1 has a data state of "1". In this case, since the control gate potential V.sub.CG of the memory cell M2 is 12.5 V, the floating gate potential V.sub.FG is 10.5 V according to equation (5). However since the erasing gate potential is set at 5 V, the potential of the erasing gate viewed from the floating gate, is -5.5 V. If a voltage of 5 V is applied to the erasing gate in this manner, the electric field of the floating gate of the non-selected cell on the same word line as that of the selected cell is reduced with respect to the erasing gate, and reliability against an erroneous operation due to erroneous write operation can be increased. FIG. 5 collectively shows voltage stresses of the erasing gates acting on the floating gates of the four memory cells M1 to M4. Referring to FIG. 4, when the non-selected memory cells M3 and M4 connected to the word line WL2, different from the word line of the selected memory cell, have a data state of "0", the voltage stress of the erasing gate acting on the floating gate becomes maximum. As is apparent from FIG. 5, in the non-selected cells M3 and M4, a voltage of +8 V is applied between the floating gate and the erasing gate to form a weak erasing state, and electrons in the floating gate tend to be emitted to the erasing gate, thus causing erroneous erasure.
FIG. 6 is a circuit diagram showing an arrangement of a conventional semiconductor memory using the abovedescribed memory cells. The drain of each cell 30 of a memory cell array 31 in FIG. 6 is connected to either of n data lines DL1 to DLn, and its control gate is connected to either of m word lines WL1 to WLm. At the same time, the erasing gates of all the memory cells are commonly connected to an erase line EL. A voltage of, e.g., 0 V is applied to the source of each memory cell. In this case, since the erasing gates of all the memory cells 30 in the memory cell array 31 are commonly connected, the voltage V.sub.EG is applied to the erasing gates of all the memory cells 30 in the data write mode. Referring to FIG. 6, reference numeral 32 denotes a row decoder; 33, a column decoder; 34-1 to 34-n, column selection transistors; 35, a bus line; 36, a data input circuit; 37, a sense amplifier circuit; 38, a data output circuit; 39, a boost-up circuit for data erasing; and 41, an address buffer.
A case wherein a data write time per cell is represented by t and all the bits are written will be considered. In a non-selected state, a maximum stress time in a weak erasing state in which each control gate is set at 0 V (described with reference to FIG. 5) is {(m-1).times.n}.times.t (m is the number of row lines and n is the number of column lines) per bit.
As described above, in the conventional semiconductor memory shown in FIG. 6, in the data write mode, when a high voltage is applied to the drain and the control gate of a given memory cell 30 with its source and the substrate being set at "0"level, and hot electrons are injected in the floating gate, a voltage of 5 V is also applied to the erasing gate.
As a result, in FIG. 3, the voltage V.sub.FG rises to a certain potential by a value corresponding to the capacitance C.sub.FE. For this reason, the write speed is increased to improve write efficiency. That is, the write speed per memory cell is increased, and hence the write speed of the overall memory is increased. The conventional semiconductor memory reduces an erroneous write stress on a non-selected cell on the same word line.
In contrast to this, in spite of the fact that the control gate of a non-selected cell on a word line different from that of a selected cell is set at 0 V, since the voltage V.sub.EG is applied to its erasing gate, the field intensity of the erasing gate with respect to the floating gate becomes larger than that of a non-selected cell on the same word line as that of the selected cell. Therefore, erroneous erasure tends to occur. In addition, the probability of erroneous erasure is increased in proportion to the voltage stress time. This stress time depends on the storage capacity of the memory. The stress time is prolonged with an increase in storage capacity of the memory, thus posing a problem in terms of reliability. For example, in a 1 M-bit (128 K words.times.8 bits) memory, n=128 and m=1,024 (in FIG. 6). If a write time per bit is 1 ms, the maximum time during which an erroneous write stress acts on a given non-selected cell on the same word line as that of a selected cell is: EQU 1 ms.times.127=127 ms
and, the maximum time during which an erroneous stress acts on a given non-selected cell on a word line different from that of the selected cell becomes very long as follows: EQU 1 ms.times.(1,024-1).times.128=130,944 ms.apprxeq.131 s.